1. Field of the Invention
The present invention relates to a semiconductor device which can be used as a superfast bipolar transistor integrated circuit or the like.
2. Description of the Related Art
There has recently been proposed a bipolar transistor integrated circuit which is produced by a trenching isolation process which produces desired isolation of component elements by forming a sectionally V-shaped or U-shaped deep ditch or trench in an element isolating region of the circuit.
FIG. 4 illustrates principal portions of a conventional bipolar transistor integrated circuit manufactured by employing such a trenching isolation process. In this structure, a silicon semiconductor body 1 is formed by epitaxially depositing on a p-type silicon substrate 2, for example, an n-type semiconductor layer 3 which serves as a collector buried region. A high-resistivity n-type semiconductor layer 4 serves as a collector region. Subsequently an element isolating trench 5 is formed in the semiconductor body 1 and, then the inner surfaces of trench 5 are oxidized to form a silicon dioxide (SiO.sub.2) film 6 after which a polycrystal silicon layer 7 and a silicon dioxide layer 8 are buried in the trench 5 to form a trenched element isolating region 9.
Also shown are a p-type base region 10, a p.sup.+ base contact region 11, an n-type emitter region 12, and a field oxide layer 13 which is formed by selective oxidation (LOCOS).
The p.sup.+ base contact region 11 is formed by diffusion of boron (B) or the like from a polycrystal silicon layer 14 which is doped with a p-type impurity such as boron, and the polycrystal silicon layer 14 is sued as a leadwire for the base electrode 15. The emitter region 12 is formed by diffusion of arsenic (As) or the like from a polycrystal silicon layer 16 which is doped with an n-type impurity such as arsenic, and an emitter electrode 17 is formed on the polycrystal silicon layer 16. Although not shown, a collector electrode is formed to connect to the collector buried region 3. A silicon layer 18 separates layers 14 and 16.
During the forming of the p.sup.+ base contact region 11, the silicon dioxide layer 8a on the body 1 including the isolating region 9 is first patterned, then the boron-doped polycrystal silicon layer 14 which is deposited thereon is patterned, and subsequently a heat treatment process is executed. During this stage, there may be performed a process of entirely removing the silicon dioxide layer 8a by etching. However, such a technique also causes a partial removal of the inner silicon dioxide layer 8 which exists in the trench 5 which will consequently cause a level difference. The level difference has a harmful influence on the subsequent process steps. So as to eliminate this problem, the silicon dioxide layer 8a is provided to maintain a flat surface.
In the bipolar transistor shown in FIG. 4, it is necessary to reduce the capacitance C.sub.CB between the collector and the base so as to obtain fast operation. Such capacitance C.sub.CB is determined principally by the sum of the p.sup.+ -n junction capacitance C.sub.1 in the base contact region 11 and the capacitance between the polycrystal silicon layer 14 and the collector region 4 with the silicon dioxide layer 8a interposed, i.e. the MIS capacitance C.sub.2 under the leadwire for the base. (C.sub.CB =C.sub.1 +C.sub.2.) Even if the p.sup.+ -n junction capacitance C.sub.1 is reduced by self-alignment, the contribution of the MIS capacitance C.sub.2 will still not be negligible.
The effective reduction of the MIS capacitance C.sub.2 may be achieved by reducing the distance x between the p.sup.+ base contact region 11 and the element isolating region 9. However, it is known that a dimensional tolerance of 0.2 to 0.3 micron is the limit for the distance x between the p.sup.+ base contact region 11 and the element isolating region 9.
Due to the level difference, the thickness y of the silicon dioxide layer 8a is restricted to 0.1 micron or so and cannot be increased.